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Adaptive Hardware Architecture for Neural-Network-on-Chip
dc.contributor.author | Khalil, Kasem | |
dc.contributor.author | Dey, Bappaditya | |
dc.contributor.author | Kumar, Ashok | |
dc.contributor.author | Bayoumi, Magdy | |
dc.date.accessioned | 2022-10-14T02:52:50Z | |
dc.date.available | 2022-10-14T02:52:50Z | |
dc.date.issued | 2022 | |
dc.identifier.other | WOS:000861351300029 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/40568 | |
dc.source | WOS | |
dc.title | Adaptive Hardware Architecture for Neural-Network-on-Chip | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Dey, Bappaditya | |
dc.contributor.orcidimec | Dey, Bappaditya::0000-0002-0886-137X | |
dc.identifier.doi | 10.1109/MWSCAS54063.2022.9859323 | |
dc.identifier.eisbn | 978-1-6654-0279-8 | |
dc.source.numberofpages | 4 | |
dc.source.peerreview | yes | |
dc.source.conference | IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS) | |
dc.source.conferencedate | AUG 07-10, 2022 | |
dc.source.conferencelocation | Fukuoka | |
imec.availability | Under review |
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