At the Extreme of 3D-NAND Scaling: 25 nm Z-Pitch with 10 nm Word Line Cells

Abstract

A 25 nm pitch 3D-NAND gate-all-around macaroni device with 10 nm gate length, is structurally and electrically demonstrated for the first time. The key fabrication process steps enabling the scaled devices are discussed, such as TiN metal fill and Al2O3 deposition inside the memory hole. We show that an appropriate biasing scheme can reduce the detrimental impact of neighbor-induced barrier lowering on both the transistor characteristics and the memory operation, achieving a -4 V VT and STS of 0.3 V/ dec and a memory window of 7 V. Reliability is not significantly impacted at scaled pitches. This study provides a basis for fabrication and understanding of future ultra-high bit density 3D-NAND memories.