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Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: process window versus complexity

dc.contributor.authorAugendre, Emmanuel
dc.contributor.authorRooyackers, Rita
dc.contributor.authorCaymax, Matty
dc.contributor.authorVandamme, Ewout
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorPerello, Carles
dc.contributor.authorVan Dievel, Marc
dc.contributor.authorPochet, Sandrine
dc.contributor.authorBadenes, Gonçal
dc.date.accessioned2021-10-14T12:39:56Z
dc.date.available2021-10-14T12:39:56Z
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4077
dc.sourceIIOimport
dc.titleElevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: process window versus complexity
dc.typeJournal article
dc.contributor.imecauthorCaymax, Matty
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.imecauthorVan Dievel, Marc
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage1484
dc.source.endpage1491
dc.source.journalIEEE Trans. Electron Devices
dc.source.issue7
dc.source.volume47
imec.availabilityPublished - open access


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