Gate patterning development for monolithic CFET integration

Abstract

Complementary field effect transistors (CFET) consist in stacking NMOS and PMOS transistors on top of each other to gain further area and continue device scaling. With this 3D stacking approach, very high-aspect ratio and vertical features are requested and create process challenges for nanosheet (NSH), gate, spacer source/drain cavity and contact patterning [1]. For the gate, the challenge lies with the tight gate pitches and taller gates induced by an increase of NSH stack height. This raises some concerns regarding NSH erosion (breakthrough of the gate oxide and recess of top Si/SiGe NSH) and gate CD/profile control. A highly directional gate etch process with an infinite selectivity to the thin dummy gate oxide liner is therefore mandatory. In this presentation, we will discuss the dummy gate etch development in a monolithic CFET integration. Gate patterning was achieved in a 45-50 nm gate pitch range using EUV single print. Figure 1 shows a morphological demonstration of gate on NSH patterning with straight gate profile, minimal NSH attack (~2 nm) and STI recess for a 75nm NSH stack. We will also analyze the effect of some plasma parameters in view of patterning higher aspect ratio gates (up to 20 including the hard mask) with NSH stack height up to 120 nm. Reference: [1] N. Horiguchi et al. "Patterning challenges and opportunities in nanosheet device architectures", Proc. SPIE PC12056, Advanced Etch Technology and Process Integration for Nanopatterning XI, PC1205608 (13 June 2022); https://doi.org/10.1117/12.2615984