On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors

Abstract

We simulate relative changes of the saturation drain current during hot-carrier degradation (HCD) in dynamically-doped (D-2) and "traditional" planar complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) of gate lengths and doping profiles. To achieve this goal, we use our physics-based model for HCD validated against experimental data from a broad range of transistor architectures (which include but are not limited to planar, fin, and nanowire FETs). These simulations show that at lower gate voltages of V-gs <= 0.9 V (i.e. covering the operating regime) D-2 FETs have superior HC reliability compared to their CMOS counterparts, while at V-gs >= 1.0 V the CMOS FET begins to be more reliable (at shorter stress times, however, the D-2 device is still superior). Under these low stress voltages, HCD is governed by the multiple-carrier process of bond dissociation controlled by the carrier concentration (rather than energy), which has different V-gs dependences in D-2 and CMOS FETs. Based on conducted calculations, we suggest that, in addition to better performance and scalability compared to the CMOS counterpart, the D-2 FET has also superior hot-carrier reliability.