Nanopore field-effect transistors with steep slope characteristics

Abstract

The solid-state nanopore field-effect transistor (NPFET) is a proposed upgraded nanopore for the realization of single molecule detection. The NPFET [1-4] detects the motion of a molecule running through the nanopore making use of the transistor’s electronic current. It therefore promises to allow the analysis of translocating molecules for genomics, proteomics, and DNA memory, with higher bandwidth readout, higher throughput, and high accuracy. In this work, we report a milestone of fabrication and characterization of the NPFET. The lithography based nanopore formation and opening in the nanowire channel is realized, with nanopore diameter down to 20-30 nm, and silicon channel as narrow as 4 nm. The process is shown in Figure 1. The device geometric features were imaged by top-view SEM (Scanning Electron Microscopy, Figure 2) and by cross-sectional and longitudinal TEM (Transmission Electron Microscopy, Figure 3). In these images, it is clear that both the top reservoir, and the nanopore embedded in the nanowire channel were successfully opened. The electrical characterization was carried out by immersing the NPFET in 0.1xPBS solution. A PTFE flow cell with silicone gaskets is mounted on the NPFET sample, and PTFE and PVC tubing connect the flow cell to a flow-through Ag/AgCl reference electrode which is used to electrolytically gate the devices. The NPFET sample with flow cell is placed in a probe station to electrically characterize the NPFET. The measurement setup is shown in Figure 4. The measured transfer characteristics (Ids-Vgs) and output characteristics (Ids-Vds) are shown in Figure 5 and Figure 6 respectively. The NPFET has excellent sub-threshold swing (SS) properties, with some of the best devices showing SS approaching the 60 mV/dec limit. Moreover, no hysteresis and drain-induced barrier lower (DIBL) was observed. The on-state current and peak transconductance is larger than 1 mA/m and 1 mS/m respectively which means these devices can realize high performance and good off-states properties simultaneously. We attribute the realization of near ideal SS of the NPFET on one hand to the high-quality narrow silicon channel (as shown in Figure 3, right) and the strong local gate control due to the nanopore embedded in the channel. Proper wetting of the nanopore in the electrolyte gate measurement is also crucial for achieving this ideal SS. We simulated the electrical characteristics using GTS Global TCAD Solutions (a commercial TCAD simulator) with completely wetted and completely unwetted nanopores which is shown in Figure 7 (Simulated NPFET structure) and Figure 8 (Extracted SS from simulated Id-Vg curves). The results show that for the properly wetted nanopore in the nanowire channel, the SS is always below 80 mV/dec, which matches our NPFET experimental measurement results. In summary, we demonstrated the key NPFET nanopore formation process and showed excellent device characteristics with SS down to 60 mV/dec. In the future, we will demonstrate the full NPFET with both top and bottom reservoirs.