Insights into Scaled Logic Devices Connected from Both Wafer Sides

Abstract

We report on scaled finFETs connected from both wafer sides (FS & BS) for various layouts. Zero lateral distance between the buried power rail (BPR) trench - fin channel is demonstrated in a scheme also yielding straighter fin profile, beneficial for DC characteristics, with no strain or reliability impact, and exhibiting similar behavior for nTSVs set closer to the channel, down to 2CPP, and just next to (or slightly under) the fin. Comparable N/PMOS performance is obtained for thinner substrates (similar to 210 -> 110nm Si under BPR) and different routing configurations enabling both FS & BS, or BS-only measurements. Adding a lower temperature FGA after a postBS high-pressure H-2 anneal helps in V-T/EWF recovery, with reduced noise and D-it, better mobility and I-on. Also addressed is the possibility to have wider BPR by expanding it under the active area for smaller IR drop (up to similar to 12% less 98(th) percentile predicted at 2nm node design rules), exploring the self-heating impact for various configurations and an overall extension of the concept to include source contact from the backside.