Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions

Abstract

Increasing reliability concerns in advanced technologies have created a significant demand for circuit aging simulation capabilities, so that potential reliability problems can be identified and mitigated pre-production. Recognizing this need, foundries have started to provide aging models with their technology Physical Design Kits (PDK's). In this work, we present an overview of the aging models and the aging simulation methodology in the PDK of a commercial 28nm bulk technology. The unique features of this work are as follows : (i) comparison of aging model simulations with device-level measurement data obtained at a wide range of {V-gs,V-ds} conditions, and (ii) comparison of aging model simulations with circuit-level measurement data. Device- and circuit-level data are then correlated, discrepancies are identified and advantages and pitfalls of these models are highlighted.