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dc.contributor.authorBhattacharjee, Debjyoti
dc.contributor.authorMajumder, Anirban
dc.contributor.authorChattopadhyay, Anupam
dc.date.accessioned2023-08-08T08:27:16Z
dc.date.available2023-06-20T10:37:41Z
dc.date.available2023-08-08T08:27:16Z
dc.date.issued2021
dc.identifier.issn1063-9667
dc.identifier.otherWOS:000672616100009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/41983.3
dc.sourceWOS
dc.titleIn-memory realization of SHA-2 using ReVAMP architecture
dc.typeProceedings paper
dc.contributor.imecauthorBhattacharjee, Debjyoti
dc.contributor.orcidextMajumder, Anirban::0000-0001-6937-8675
dc.contributor.orcidextChattopadhyay, Anupam::0000-0002-8818-6983
dc.contributor.orcidimecBhattacharjee, Debjyoti::0000-0001-6561-8934
dc.identifier.doi10.1109/VLSID51830.2021.00013
dc.identifier.eisbn978-1-6654-4087-5
dc.source.numberofpages7
dc.source.peerreviewyes
dc.source.beginpage47
dc.source.endpage53
dc.source.conference34th International Conference on VLSI Design / 20th International Conference on Embedded Systems (VLSID)
dc.source.conferencedateFEB 20-24, 2021
dc.source.conferencelocationGuwahati
dc.source.journalna
imec.availabilityPublished - imec


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