Scaling-friendly approaches to minimize the magnitude and asymmetry of wafer warpage during 3-D NAND fabrication

Abstract

High levels of wafer warpage encountered during 3-D NAND fabrication constitute a major limitation for the advancement of the technology that relies firmly on increasing the number of layers in the vertical stack. In this study, a multi-scale finite-element modeling framework, based on local to global simulations, is utilized to identify the source and monitor the evolution of mechanical stress along with associated wafer deformations. It is shown that scaling-friendly approaches such as increasing the slit pitch and decreasing the metal layer thickness significantly reduce the magnitude and asymmetry of the warpage. Furthermore, using low-stress, low-resistivity metal replacement such as Ruthenium, alters the wafer deformation pattern from radially asymmetric to symmetric form, enabling further opportunities to minimize warpage by isotropic measures. Strategically, focusing on obtaining a symmetric deformation first, followed by applying warpage mitigation techniques is deemed to be a feasible approach. Using this method, the wafer warpage is shown to potentially reduce below 10 mu m with 128 layer 3-D NAND, thus offering a safely scalable path forward.