Sequential 3D standard cell 4T architecture using design crenellation and self-aligned MOL for N2 technology and beyond

Abstract

As traditional pitch scaling is losing steam, 3D logic is being explored to further extend density scaling as an alternative to continued standard cell scaling. This paper will discuss standard cell architectures to be used in a Sequential 3D process where the SoC is comprised out of 2 or more tiers of active CMOS with a given BEOL metal stack per tier. Using backside interconnect metals as standard cell power rails, a smart partitioning of the metal usage within standard cells can be obtained leading to 4 track cell height scaling. A design abstraction using crenelated design is however needed at block level to mitigate via and metal line end conflicts.