Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages

Abstract

Chiplet-based (2.5D and 3D) multi-die packages implement large amounts of inter-die interconnects with micro-bump connections and possibly TSVs. These interconnects can be subject to manufacturing defects. The most common defects are shorts and opens, which occur both in hard and weak (= resistive) variants. Traditional interconnect automatic test pattern generation (I-ATPG) methods only cover hard defects. These methods are generally considered efficient, as their test pattern counts scale logarithmically with the number of interconnects k. However, they cover short defects between all interconnects, including those for which shorts are unrealistic given their relative layout positions. In this paper, we propose (EITEST)-I-2, a modified True/Complement test [1], which covers, for a given collection of interconnects, all hard and weak variants of only realistic short and open defects. Supporting fault diagnosis, (EITEST)-I-2 also prevents aliasing. While it is predicted that the number of interconnects k will rise significantly in the near future, (EITEST)-I-2 provides a high-quality interconnect test for which the number of test patterns is constant and no longer dependent on k.