Evaluation of Secure Circuit Styles Using Unipolar Logic Gates

Abstract

A high level of resistance against power analysis attacks can be achieved with secure circuit styles. All existing secure circuit styles are based on CMOS logic, using both ptype and n-type transistors. However, emerging technologies, such as flexible electronics, achieve optimal price, performance and reliability with n-type-only unipolar logic gates. Therefore, in order to protect chips on flexible foil from power analysis attacks, secure circuit styles based on unipolar logic gates need to be considered. This paper presents a first step in this direction by applying the concepts of secure circuit styles, originally designed with CMOS logic in mind, to unipolar gates. The power consumption information leakage is simulated for two existing secure circuit styles, namely Wave Dynamic Differential Logic (WDDL) and Masked Dual-Rail Pre-charge Logic (MDPL). The paper shows that especially WDDL has the potential to improve the security of the design, after optimization of the transistor ratios.