A CDAC Mismatch Calibration Technique for SAR-assisted Pipeline ADCs

Abstract

This paper presents a novel on-chip CDAC mismatch calibration method for the SAR-assisted pipeline ADC. The calibration consists of mismatch detection and correction. The mismatch detection is based on the equivalent code pair generated by the capacitor bank with redundant capacitors. Each equivalent code pair produces a voltage difference that contains the mismatch information and is captured by the residue amplifier and fine-stage ADC. Then, a compensation capacitor will be added or subtracted physically to correct the mismatch error. From the worst mismatch scenario simulation in a 14-bit ADC in 65 nm CMOS technology, the SFDR and ENOB improved by 17.02 dB and 1.93 bits, respectively, after applying the proposed calibration technique.