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Design of reversible logic circuits by means of control gates

dc.contributor.authorDe Vos, Alexis
dc.contributor.authorDesoete, B.
dc.contributor.authorAdamski, A.
dc.contributor.authorPiertzak, P.
dc.contributor.authorSibinski, M.
dc.contributor.authorWiderski, T.
dc.date.accessioned2021-10-14T12:50:05Z
dc.date.available2021-10-14T12:50:05Z
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4281
dc.sourceIIOimport
dc.titleDesign of reversible logic circuits by means of control gates
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage255
dc.source.endpage264
dc.source.conferenceIntegrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. 10th Int. Workshop - PATMOS
dc.source.conferencedate16/09/2000
dc.source.conferencelocationGöttingen Germany
imec.availabilityPublished - imec
imec.internalnotesLecture Notes in Computer Science; Vol. 1918


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