dc.contributor.author | Hsu, Wen-Yang | |
dc.contributor.author | Aymerich, Joan | |
dc.contributor.author | Yang, Xiaolin | |
dc.contributor.author | Sawigun, Chutham | |
dc.contributor.author | Coppejans, Philippe | |
dc.contributor.author | Mora Lopez, Carolina | |
dc.date.accessioned | 2023-12-18T09:30:50Z | |
dc.date.available | 2023-11-12T17:45:35Z | |
dc.date.available | 2023-12-18T09:30:50Z | |
dc.date.issued | 2023 | |
dc.identifier.issn | 1930-8833 | |
dc.identifier.other | WOS:001088613100064 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/43133.2 | |
dc.source | WOS | |
dc.title | A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range | |
dc.type | Proceedings paper | |
dc.contributor.imecauthor | Hsu, Wen-Yang | |
dc.contributor.imecauthor | Aymerich, Joan | |
dc.contributor.imecauthor | Yang, Xiaolin | |
dc.contributor.imecauthor | Sawigun, Chutham | |
dc.contributor.imecauthor | Coppejans, Philippe | |
dc.contributor.imecauthor | Mora Lopez, Carolina | |
dc.contributor.orcidimec | Hsu, Wen-Yang::0000-0002-8706-0553 | |
dc.contributor.orcidimec | Yang, Xiaolin::0000-0001-9900-528X | |
dc.contributor.orcidimec | Sawigun, Chutham::0000-0001-7179-0343 | |
dc.contributor.orcidimec | Mora Lopez, Carolina::0000-0003-4200-0001 | |
dc.identifier.doi | 10.1109/ESSCIRC59616.2023.10268699 | |
dc.identifier.eisbn | 979-8-3503-0420-6 | |
dc.source.numberofpages | 4 | |
dc.source.peerreview | yes | |
dc.source.beginpage | 253 | |
dc.source.endpage | 256 | |
dc.source.conference | IEEE 49th European Solid-State Circuits Conference (ESSCIRC) | |
dc.source.conferencedate | SEP 11-14, 2023 | |
dc.source.conferencelocation | Lisbon | |
dc.source.journal | na | |
imec.availability | Published - imec | |
dc.description.wosFundingText | The authors thank Andrea Lodi for the PCB design support. This research was partially supported by the NIH grant 1U01NS115587 (Neuropixels NXT). | |