A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W

Abstract

Deep neural networks (DNNs) are widely used in applications like image recognition for high prediction accuracy. Energy efficiency, flexibility, and area efficiency are critical parameters to bring DNN capabilities to the edge. This work presents an SRAM-based digital in-memory computing matrix-vector multiplier (DiMe MVM) that provides flexibility in terms of operand bit width and efficiently accommodates different matrix sizes. Measurement results on the 28 nm CMOS chip illustrate energy and throughput benefits over other state-of-the-art digital implementations.