A novel hardware efficient design for IEEE 802.11ax compliant OFDMA transceiver

Abstract

The introduction of Multi User (MU) communication in IEEE 802.11ax in the frequency domain via MU Orthogonal Frequency Division Multiple Access (MU-OFDMA) and in the spatial domain via MU Multiple Input Multiple Output (MU-MIMO) enables the Access Point (AP) to serve up to 128 Stations (STAs) in a schedule. However, the MU functionality poses new challenges in the chip design. Existing MU Transceivers (TRXs) rely on the duplication approach wherein a dedicated hardware is utilized per user. The hardware footprint of such an approach increases proportionally with the number of users simultaneously served in the MU TRX. This paper introduces a novel hardware efficient design for an MU TRX. Unlike the duplication approach, the proposed design for the MU TRX has comparable hardware footprint of a Single User (SU) TRX regardless of the number of users being served, thanks to the hardware virtualization technique. The applicability of the design is initially validated for IEEE 802.11ax compliant MU-OFDMA transmitter on an FPGA of a modern SDR. The performance and hardware consumption is compared against the conventional duplication approach. The proof -of -concept implementation focuses on 20MHz, where maximum 9 STAs can be involved. Though we believe the design is extendable to support the maximum number of STAs in MU-OFDMA for IEEE 802.11ax standard. The experimental results show that the hardware virtualization based MU-OFDMA transmitter provides the same performance and consumes less than 13% hardware resources in comparison with the conventional duplication approach.