Study of Endurance Performance of SiO2 Interfacial Layer Scaling Through O Scavenging in Si Channel n-FeFET With Si:HfO2 Ferroelectric Layer

Abstract

By using high-speed electrical measurements, we evaluate the endurance and retention performance of the Si channel ferroelectric transistor (FeFET) having SiOx interfacial layer (IL) scaled using the oxygen scavenging technique. The interfacial SiOx is scaled from 1 to 0.4 nm by depositing a 2-nm Si capping (Si-cap) layer on the HfO2 ferroelectric layer (FL). Trapping and detrapping processes are monitored using read-disturb-free fast P - V and I-d - V-g measurements. FeFETs with a thicker (1 nm) SiO2 IL showed a similar to 2-V shift in threshold voltage ( V-th) postprogramming pulse due to trapping in and around the IL, resulting in similar to 1-s write-to-read delay. The addition of Si-cap eliminated read-after-write delay in the pristine state, which is attributed to the shorter tunneling distance for the traps in the IL and near the FL-IL interface. The endurance cycling was found to degrade subthreshold swing (SS) and shift V-th in the without Si-cap (w/o Si-cap) devices, suggesting the generation of both interface states and bulk defects. The addition of Si-cap was found to help reduce the generation of interface states and the bulk FL defects owing to the lower effective electric field. It was also found that fatigue cycling introduces a read-after-write delay in the Si-cap (w/Si-cap) devices, which points to the generation of defects near the FL:IL interface. Even though the endurance and read-after-write delay performance improved, the tradeoff is higher depolarization due to a partially oxidized paraelectric Si-cap layer in series with the FL in the devices w/Si-cap. Our study shows that avoiding the formation of SiOx IL and improving the quality of the FL are critical for improving both retention and endurance performance in Si channel FeFETs.