An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime

Abstract

In this article, an approach for the development of a digital standard cell library design is proposed with 28 nm Fully Depleted Silicon-on-Insulator (FDSOI) technology for Near Threshold Voltage (NTV) regime at multiple V-DD Points. A new systematic sizing approach is proposed with the utilization of biasing features such as poly biasing and body biasing related to a transistor. These features facilitate high-energy efficiency and optimized performance. Due to the excellent response with lower process variations and leakage reduction, a 28 nm-FDSOI process node is used for this work. The proposed standard cell library is designed by incorporating asymmetric biasing techniques and achieved minimum process variations while employing in ring oscillators (RO) and buffer circuitry. The newly developed library results in 42% and 35% of delay and energy reduction, respectively.