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dc.contributor.authorMazaya, Muhammad Sulthan
dc.contributor.authorBudi, Eko Mursito
dc.contributor.authorSyafalni, Infall
dc.contributor.authorSutisna, Nana
dc.contributor.authorAdiono, Trio
dc.date.accessioned2024-08-12T08:18:39Z
dc.date.available2024-07-28T19:32:52Z
dc.date.available2024-08-12T08:18:39Z
dc.date.issued2024
dc.identifier.isbn979-8-3503-8415-4
dc.identifier.issn2473-4683
dc.identifier.otherWOS:001229693800003
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/44210.2
dc.sourceWOS
dc.titleReinforcement Learning Hardware Accelerator using Cache-Based Memoization for Optimized Q-Table Selection
dc.typeProceedings paper
dc.contributor.imecauthorSyafalni, Infall
dc.contributor.imecauthorSutisna, Nana
dc.contributor.orcidimecSyafalni, Infall::0000-0001-9922-5688
dc.contributor.orcidimecSutisna, Nana::0000-0002-8435-9242
dc.identifier.doi10.1109/COOLCHIPS61292.2024.10531164
dc.identifier.eisbn979-8-3503-8414-7
dc.source.numberofpages6
dc.source.peerreviewyes
dc.source.conferenceSymposium in Low-Power and High-Speed Chips (COOL CHIPS)
dc.source.conferencedateAPR 17-19, 2024
dc.source.conferencelocationTokyo
dc.source.journalN/A
imec.availabilityPublished - imec
dc.description.wosFundingTextThis work is supported by the 2024 Bandung Institute of Technology Research Program (Riset-ITB 2024). The authors also thank the School of Electrical Engineering and Informatics and the Faculty of Industrial Engineering, Bandung Institute of Technology for their support. M. S. Mazaya thanks IEEE Cool Chips 27 for the student travel grants.


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