Demonstration of Chip Overclock Detection by Employing Tamper-Aware Odometer Technology

Abstract

Integrated circuits (IC) are the heart of all electronic systems in critical sectors like automotive, aerospace, or healthcare, in key infrastructures like telecommunications, energy, or data centers, as well as in consumer electronics. In all these environments, ICs are designed to offer optimal performance during their intended lifetime. Sometimes, performance-boosting techniques, such as chip frequency overclocking, are used to accelerate data computation and throughput, which can impact the lifetime of the chip. In this scenario, the use of these techniques, in addition to regular chip operation, could critically accelerate IC degradation, reducing drastically the intended performance and lifetime of the ICs. For this reason, on-chip degradation monitors have recently gained significant relevance because they can provide real-time projection of IC reliability by exploiting the fundamental physics of BTI and HCD circuit degradation. In this work, we study the impact of a typical overclock operation on a chip fabricated on a 0.9 V 28 nm HKMG foundry technology. We first prove that such overclock will not result in any observable degradation of the digital circuitry of the chip. However, we demonstrate that our latest odometer technology can unequivocally expose those overclock stress conditions, thus detecting degradation of the chip that might have remained undetected otherwise.