CMOS Scaling by Nanosheet Device Architectures and Backside Engineering

Abstract

Nanosheet device is being introduced in the industry as post-FinFET CMOS device architecture thanks to its wider transistor effective width/footprint by stacked nanosheet channels. Nanosheet device scaling will continue by combining slow pitch/track scaling and device architecture evolutions, such as Forksheet and CFET. Backside power delivery combined with nanosheet device architectures is expected to provide smaller IR drop and better scalability. It can be extended to functional backside, which contains variety of components at backside for further system-on-chip scaling/performance improvement.