Test and Repair Improvements for UCIe

Abstract

The success of chiplet-based design critically depends on standards, especially those for die-to-die interconnects. Universal Chiplet Interconnect Express (UCIe) is such a standard, showing promising potential in its field. Among other things, UCIe standardizes the micro-bump map. It incorporates several spare interconnects able to "repair" defective interconnects. We outline a very efficient, aliasing-free test generation method for all hard and weak short and open manufacturing defects on die-to-die interconnects that uses just 16 test patterns, irrespective of the number of interconnects. We also propose to improve repairability of the UCIe interconnects through reorganizations of the micro-bump map that eliminate the risk for non-repairable ('catastrophic') defects and minimizes the usage of spare interconnects. The micro-bump map reorganizations are not backwards compatible and hence, since UCIe is still in its early stages of actual usage, it would be best to incorporate this improvement in the standard as soon as possible.