A 32 Gb/s Full duplex Bi-directional Transceiver with Crosstalk Cancellation for Chiplet Interconnections

Abstract

Leveraging advanced packaging technology can further improve chip integration by minimizing the dimensions of chip-to-chip interconnections at chiplet interfaces. Nonetheless, the escalation of crosstalk noise, driven by increased speed and routing density, poses a threat to chip functionality. This paper explores the effects of crosstalk in systems through channels with varied lengths and spacings. It also introduces a new high-speed bi-directional transceiver architecture designed to mitigate crosstalk in chiplets or systems featuring short channels and multiple inputs/outputs. Implemented using a 12-nm FinFET process, the proposed transceiver achieves an energy efficiency of 0.46 pJ/bit while operating at 32 Gb/s across a 5-mm channel with 1-μm spacing.