Interconnect Delay Modeling of Critical Paths in Angstrom Nodes

Abstract

This work provides a methodology to analyze and model critical path interconnections of physically implemented digital designs in Angstrom nodes. The Elmore delay computation is applied to the detailed interconnect topology to provide a block-level statistical assessment of dominant parameters such as wire and via resistance (R), as well as wire and pin capacitance (C), on interconnect performance. Our methodology can rapidly assess the impact of back-end-of-line (BEOL) materials, interconnect geometries, and scaling boosters on the interconnect delay of complex digital designs, enabling fast turn-around time for Design-Technology Co-optimization (DTCO) loops. The model predicts delays with 1.3 percent of maximum mean error, standard deviations below 3 percent, and 23x speedups compared to conventional Static-Timing-Analysis (STA) sensitivity analyses.