Analysis of inverter architectures in a GaN-IC technology

Abstract

The effectiveness of GaN-IC technology for power electronics depends on the seamless integration of high-power devices and peripheral circuits. Peripheral circuitry architecture dictates performance and competitiveness. The absence of a well-performing p-type device compels adoption of resistor-transistor logic (RTL) and direct-coupled field effect transistor logic (DCFL) architectures for analog building blocks in designing fully integrated GaN-IC circuits. It is therefore crucial to evaluate the trade-offs of each architecture. This paper analyzes the performance of three inverter architectures in a GaN-IC platform: one type is based on RTL and two other types based on DCFL. In addition to the enhancement mode (E-mode) high-electron-mobility transistor (HEMT) as the driver, the RTL architecture uses a 2-Dimensional Electron Gas (2DEG) layer as resistor load, whereas the DCFL architecture uses a gate-source shorted depletion mode (D-mode) HEMT as the load. There are two choices for the D-mode device: the D-mode metal-insulator-semiconductor (MIS) HEMT and the D-mode pGaN island HEMT. For a thorough comparison, key performance metrics such as noise margins, rise/fall times, average power consumption, propagation delay, threshold voltage, and the architectures' footprint are analyzed. The trade-offs of each architecture are analyzed by varying the size of driver and load devices to understand their effect on the various inverter performance metrics. Understanding these metrics and their relationship with device parameters aids in selecting the most suitable architecture for intended application.