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Effects of global interconnect optimizations on performance estimation of deep submicron design

dc.contributor.authorCao, Y.
dc.contributor.authorHu, C.
dc.contributor.authorHuang, X.
dc.contributor.authorKahng, A.B.
dc.contributor.authorMuddu, S.
dc.contributor.authorStroobandt, D.
dc.contributor.authorSylvester, D.
dc.date.accessioned2021-10-14T14:26:06Z
dc.date.available2021-10-14T14:26:06Z
dc.date.issued2000
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/4980
dc.sourceIIOimport
dc.titleEffects of global interconnect optimizations on performance estimation of deep submicron design
dc.typeProceedings paper
dc.source.peerreviewno
dc.source.beginpage56
dc.source.endpage61
dc.source.conferenceIEEE/ACM International Conference on Computer Aided Design - ICCAD
dc.source.conferencelocation
imec.availabilityPublished - imec


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