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Ultrathin (< 4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits

dc.contributor.authorGreen, Martin
dc.contributor.authorGusev, E. P.
dc.contributor.authorDegraeve, Robin
dc.contributor.authorGarfunkel, E. L.
dc.date.accessioned2021-10-14T16:59:14Z
dc.date.available2021-10-14T16:59:14Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5321
dc.sourceIIOimport
dc.titleUltrathin (< 4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: understanding the processing, structure, and physical and electrical limits
dc.typeJournal article
dc.contributor.imecauthorDegraeve, Robin
dc.source.peerreviewno
dc.source.beginpage2057
dc.source.endpage2121
dc.source.journalJournal of Applied Physics
dc.source.issue5
dc.source.volume90
imec.availabilityPublished - imec


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