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A simulation evaluation of 100 nm CMOS device performance

dc.contributor.authorJones, S. K.
dc.contributor.authorBazley, D. J.
dc.contributor.authorAugendre, Emmanuel
dc.contributor.authorBadenes, Gonçal
dc.contributor.authorDe Keersgieter, An
dc.contributor.authorSkotnicki, T.
dc.date.accessioned2021-10-14T17:07:06Z
dc.date.available2021-10-14T17:07:06Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5381
dc.sourceIIOimport
dc.titleA simulation evaluation of 100 nm CMOS device performance
dc.typeProceedings paper
dc.contributor.imecauthorDe Keersgieter, An
dc.contributor.orcidimecDe Keersgieter, An::0000-0002-5527-8582
dc.source.peerreviewno
dc.source.beginpage288
dc.source.endpage291
dc.source.conferenceProceedings of the International Conference on Simulation of Semiconductor Physics and Processes - SISPAD
dc.source.conferencedate5/09/2001
dc.source.conferencelocationAthens Greece
imec.availabilityPublished - imec


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