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Memory hierarchy layer assessment for data re-use exloitation in multimedia algorithms realized on predefined processor architectures

dc.contributor.authorMasselos, Kostas
dc.contributor.authorCatthoor, Francky
dc.contributor.authorKakarudas, A.
dc.contributor.authorGoutis, C. E.
dc.contributor.authorDe Man, Hugo
dc.date.accessioned2021-10-14T17:19:25Z
dc.date.available2021-10-14T17:19:25Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5470
dc.sourceIIOimport
dc.titleMemory hierarchy layer assessment for data re-use exloitation in multimedia algorithms realized on predefined processor architectures
dc.typeProceedings paper
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorDe Man, Hugo
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage285
dc.source.endpage288
dc.source.conferenceProceedings International Conference on Electronic Circuits and Systems - ICECS; September 2001; Malta.
dc.source.conferencelocation
imec.availabilityPublished - imec


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