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Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

dc.contributor.authorMiranda, Miguel
dc.contributor.authorGhez, Cédric
dc.contributor.authorKulkarni, Chidamber
dc.contributor.authorCatthoor, Francky
dc.contributor.authorVerkest, Diederik
dc.date.accessioned2021-10-14T17:20:47Z
dc.date.available2021-10-14T17:20:47Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5479
dc.sourceIIOimport
dc.titleSystematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications
dc.typeProceedings paper
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorVerkest, Diederik
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.contributor.orcidimecVerkest, Diederik::0000-0001-6567-2746
dc.source.peerreviewno
dc.source.beginpage107
dc.source.endpage112
dc.source.conferenceProceedings 14th International Symposium on System Synthesis
dc.source.conferencedate30/09/2001
dc.source.conferencelocationMontreal Canada
imec.availabilityPublished - imec


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