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200 MBit/s 4-symbol arithmetic encoder architecture for embedded zero tree-based compression

dc.contributor.authorOsorio, Roberto
dc.contributor.authorVanhoof, Bart
dc.date.accessioned2021-10-14T17:32:55Z
dc.date.available2021-10-14T17:32:55Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5557
dc.sourceIIOimport
dc.title200 MBit/s 4-symbol arithmetic encoder architecture for embedded zero tree-based compression
dc.typeProceedings paper
dc.source.peerreviewno
dc.source.beginpage397
dc.source.endpage405
dc.source.conferenceProceedings IEEE workshop on Signal Processing Systems - SIPS
dc.source.conferencedate26/09/2001
dc.source.conferencelocationAntwerpen
imec.availabilityPublished - imec


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