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Efficient implementation of pipelined 2D-DCT processor using single 1D-FFT block

dc.contributor.authorPasko, Robert
dc.contributor.authorMarescaux, Théodore
dc.contributor.authorRynders, Luc
dc.contributor.authorVernalde, Serge
dc.date.accessioned2021-10-14T17:34:22Z
dc.date.available2021-10-14T17:34:22Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5566
dc.sourceIIOimport
dc.titleEfficient implementation of pipelined 2D-DCT processor using single 1D-FFT block
dc.typeProceedings paper
dc.contributor.imecauthorRynders, Luc
dc.contributor.imecauthorVernalde, Serge
dc.source.peerreviewno
dc.source.beginpage41
dc.source.endpage44
dc.source.conference3rd Electronic Circuits and Systems Conference; September 2001; Bratislava, Slovakia.
dc.source.conferencelocation
imec.availabilityPublished - imec


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