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Ultra thin chip vertical integration technique

dc.contributor.authorPinel, S.
dc.contributor.authorTasselli, J.
dc.contributor.authorLepinois, F.
dc.contributor.authorMarty, A.
dc.contributor.authorBailbe, J. P.
dc.contributor.authorBeyne, Eric
dc.contributor.authorVan Hoof, Rita
dc.contributor.authorMarco, S.
dc.contributor.authorMorante, J. R.
dc.date.accessioned2021-10-14T17:36:41Z
dc.date.available2021-10-14T17:36:41Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5580
dc.sourceIIOimport
dc.titleUltra thin chip vertical integration technique
dc.typeProceedings paper
dc.contributor.imecauthorBeyne, Eric
dc.contributor.imecauthorVan Hoof, Rita
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewno
dc.source.beginpage299
dc.source.endpage302
dc.source.conferenceConference Proceedings of the 13th European Microelectronics and Packaging Conference & Exhibition; 30 May - 1 June 2001; Stras
dc.source.conferencelocation
imec.availabilityPublished - imec


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