Unified Analysis of Time-Dependent Dielectric Breakdown to Extend Reliability Margins

Abstract

As VLSI technology continues to scale, the gate-oxide time-dependent dielectric breakdown (TDDB) reliability margins are progressively diminishing. In fact, present-day industry-established TDDB reliability projection methodologies based on maximum allowed gate overdrive voltage can predict none to negative margins, in clear contrast to reality. This chasm necessitates a thorough revision of the traditional lifetime extraction methods and TDDB modeling, based on a more detailed and comprehensive understanding of this complex failure mechanism. In this article, we consolidate, update, and integrate existing knowledge into a new, unified state-of-the-art framework. We demonstrate that by accurately estimating the parameters describing all phases of gate-oxide TDDB, i.e., the soft-breakdown (SBD), the wear-out (WO), and the hard-breakdown (HBD), along with the current flowing through a single leakage path, gate leakage both in a single device and in the entire chip can be projected for any (operating) voltage and time. Gate leakage impact on individual circuits and the total power dissipation thus become critical parameters, providing a new, revised perspective on TDDB lifetime projection methodology and simultaneously resulting in more realistic, enhanced TDDB reliability margins in devices with aggressively scaled gate oxides.