I/O Circuit and Sub-5V ESD Protection for Advanced Bonding Interfaces

Abstract

This study investigates the impact of electrostatic discharge (ESD) protection on the performance of I/O circuits in 2.5D-chiplet and 3D integrated architectures, focusing on 12-nm FinFET devices. Using 1-ns-pulse ESD stress measurements and S-parameter analysis, it assesses trade-offs between ESD protection effectiveness and the corresponding capacitance and layout area penalties. The findings highlight the challenges of optimizing chiplet interconnects while meeting evolving protection standards. However, as ESD protection capacitance exceeds interconnect capacitance, it introduces severe RC delay penalties, making further reductions in protection levels essential for maintaining system efficiency and integration feasibility.