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Shallow junctions for sub-100 nm CMOS technology

dc.contributor.authorMeyssen, Veerle
dc.contributor.authorStolk, Peter
dc.contributor.authorvan Zijl, Jeroen
dc.contributor.authorvan Berkum, Jurgen
dc.contributor.authorvan de Wijgert, Willem
dc.contributor.authorLindsay, Richard
dc.contributor.authorDachs, Charles
dc.contributor.authorMannino, Giovanni
dc.contributor.authorCowern, Nick
dc.date.accessioned2021-10-14T18:35:35Z
dc.date.available2021-10-14T18:35:35Z
dc.date.issued2001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/5890
dc.sourceIIOimport
dc.titleShallow junctions for sub-100 nm CMOS technology
dc.typeProceedings paper
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpageJ.3.5.1
dc.source.endpageJ3.5.6
dc.source.conferenceSi Front-End Processing - Physics and Technology of Dopant-Defect Interactions III
dc.source.conferencedate17/04/2001
dc.source.conferencelocationSan Francisco, CA USA
imec.availabilityPublished - open access
imec.internalnotesMaterials Research Society Symposium Proceedings; Vol. 669


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