Optimized Two Metal Level Semi-Damascene Interconnects For Superconducting Digital Logic

Abstract

In this work, we present an optimized two-metal level (2ML) BEOL unit process based on NbTiN developed in imec’s 300mm pilot line. Vias with varying critical dimension (CD), pre-clean conditions, and metal fill depositions were explored to mitigate the formation of voids in the vias upon PVD deposition into the cavities. A range of via CDs down to 40 nm were produced using lithography bias. NbTi alloy target deposition improved wafer resistivity relative standard deviation by 50% compared to co-sputtering, improving wafer uniformity. Different integration routes were evaluated to fabricate NbTiN wires while minimizing sidewall oxidation and electrical CD losses. Critical currents were up to 2x better than previously reported via-chain devices. Wire CD loss was reduced by at least 7 nm. Wire critical currents are similar for top and bottom layers, indicating no degradation with additional processing. The critical current density is up to 95 mA/pm2, which is greater than half of the theoretical depairing current density of our thin films.