Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure

Abstract

This article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash scripting. The method involves creating an effective current source model (ECSM) .libs file with a custom tool flow, which incorporates variation-aware timing models of standard cells to minimize recharacterization efforts. The resulting file is integrated into an industry-standard STA tool environment to assess the impact of device and layout level variability on digital timing closure. The simulation work is carried out using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime STA environment in STMicroelectronics (STM) 65 nm CMOS process. This tool flow reduces recharacterization efforts by 98.13% compared to conventional SPICE simulation by incorporating the impact of device-level variability on the conventional STA flow.