Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy

Abstract

As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requires characterization methods capable of mapping active carriers with nanometer-scale resolution. This work demonstrates a significant advancement in scanning spreading resistance microscopy (SSRM) that enables, for the first time, carrier mapping within 5.5 nm thick nanosheet channels. This was achieved through a systematic optimization of sample preparation to achieve sub-nanometer topography, the use of ultra-sharp diamond probes, and the implementation of a linear current amplifier to eliminate artifacts from slow logarithmic amplifiers. SSRM measurements of NSFETs with and without a 950°C rapid thermal anneal reveal a clear increase in phosphorus diffusion due to the higher thermal budget, with carrier profiles in excellent agreement with Kinetic Monte Carlo process simulations. This demonstrates how SSRM is a valuable characterization technique for providing direct feedback on junction formation in advanced gate-all-around devices.