Thermal Impact of BSPDN for 3D Memory on Logic integrantion

Abstract

In this study, we conduct a comparative thermal impact analysis of BSPDN and FSPDN across various 3D integration schemes, involving both logic and memory components. The thermal effects are assessed for face-to-face (F2F) and back-to-face (B2F) bonding assemblies, as well as for a difference in the order of the components in the stack, specifically logic-on-top and memory-on-top arrangements. The analysis is furthermore extended to multiple memory tiers on logic. The results showed that 3D SoC BSPDN present a lower thermal penalty compared with 2D SoC, due to the similar material layers in 3D SoC for FSPDN and BSPDN. While the bonding assembly presents limited effect on the temperature increase, the order of the logic and memory die in the stack presents a larger impact on the thermal performance of 3D SoC stacks. In this case, the logic on top configuration is thermally limited by the memory die temperature, while for the memory-on-top configuration, the logic temperature is the limiting factor. Multi-tier memory on logic stack required a more complex thermal management. High performance cooling significantly improves the temperature in the stack allowing for high power dissipation.