Direct die-to-wafer bonding on thin interposers: Wafer reconstruction and back side nanotopography evaluation

Abstract

Several chip-on-interposer flows are discussed. Although a chip first-interposer last flow can be considered more mature in high volume consumer applications compared to an interposer first-chip last flow, the latter can be more beneficial in high performance and yield-critical applications, where reliability and electrical performance are key. Drawbacks, however, can be complexity, higher cost and higher demands on materials. Here, two such flows are evaluated in function of a temporary bonding system. Using a sequential direct die-to-wafer bonding approach, dies are stacked onto a thinned interposer, followed by over molding and die-reveal by grinding on top of the thin interposer. Minimal voiding is observed without any delamination. It is shown that large, embedded pillars generate back side topography during wafer thinning, which will require additional planarization steps before any chip assembly can be performed.