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dc.contributor.authorBeyer, Gerald
dc.contributor.authorSatta, Alessandra
dc.contributor.authorSchuhmacher, Jörg
dc.contributor.authorMaex, Karen
dc.contributor.authorBesling, Wim
dc.contributor.authorKilpela, Olli
dc.contributor.authorSprey, Hessel
dc.contributor.authorTempel, Georg
dc.date.accessioned2021-10-14T21:08:48Z
dc.date.available2021-10-14T21:08:48Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6009
dc.sourceIIOimport
dc.titleDevelopment of sub-10-nm atomic layer deposition barriers for Cu/low-k interconnects
dc.typeJournal article
dc.contributor.imecauthorBeyer, Gerald
dc.contributor.imecauthorMaex, Karen
dc.contributor.imecauthorSprey, Hessel
dc.source.peerreviewno
dc.source.beginpage233
dc.source.endpage245
dc.source.journalMicroelectronic Engineering
dc.source.issue1_4
dc.source.volume64
imec.availabilityPublished - imec
imec.internalnotesMAM2002; Vaals, The Netherlands, 3-6 March 2002


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