Show simple item record

Cu interconnects and low-K dielectrics, challenges for chip packaging

dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-14T21:08:57Z
dc.date.available2021-10-14T21:08:57Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6013
dc.sourceIIOimport
dc.titleCu interconnects and low-K dielectrics, challenges for chip packaging
dc.typeProceedings paper
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.source.peerreviewno
dc.source.beginpageMay-15
dc.source.endpageMay-17
dc.source.conferenceThe 5th International Forum on Semiconductor Technology - IFST
dc.source.conferencedate21/02/2002
dc.source.conferencelocationYokohama Japan
imec.availabilityPublished - imec


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following collection(s)

Show simple item record