High-NA EUV patterning of logic feature 20-24 nm: An e-beam defectivity analysis

Abstract

High-NA (0.55 NA) EUV lithography has emerged as a critical advancement in semiconductor patterning technology. In the early stages of the patterning process development, a systematic defectivity assessment is essential to optimize the process conditions. In this work, we use e-beam inspection tool (KLA’s eSL16TM) to characterize a single exposure highNA EUV logic place-and-route (PnR) structures, both Metal 0 (M0) and Metal 2 (M2) layers at pitches 20-24 nm. The inspection method includes high-resolution e-beam scanning on eSL16 and inline die to database (D2DB) inspection coupled with SMARTsTM deep learning algorithm for defect detection and classification. Defect counts were categorized by type, allowing us to identify which defect types limit the process window. We connect primary defect modes with the patterning variables. Eventually, this connection creates a practical pathway to optimize process parameters to reduce defects and to enable robust 20–24 nm logic PnR patterning with single exposure on high-NA EUV scanner.