A Multi-Die Self-Consistent Framework for Thermal Stability Analysis in Nanosheet 3D SiPs

Abstract

In nanosheet-era 2.5D/3D chiplet-based systems, strong temperature-dependent power introduces pronounced power-temperature feedback, rendering conventional fixed-power thermal analysis insufficient to assess thermal feasibility. In vertically integrated architectures, such temperature-induced power feedback can eliminate the existence of a stable steady-state thermal operating point, leading to thermal instability and runaway behavior that remain invisible in one-pass steady-state simulations. This work presents a multi-die self-consistent thermal analysis framework that explicitly couples temperature-dependent leakage with system-level thermal solving across heterogeneous 3D Systems-in-Package (SiPs), enabling direct evaluation of thermal stability rather than peak temperature alone. The framework is applied to a representative HPC-class SiPs integrating an N7 FinFET I/O chiplet and an A10 nanosheet compute chiplet with multiple 3D integrations, including face-to-back, face-to-face, and face-to-face with backside power delivery network (BSPDN). The results show that configurations deemed thermally feasible under fixed-power analysis can become thermally unstable once temperature-induced power feedback is considered, while enhanced package-level cooling restores convergence and exposes clear stability boundaries. These results highlight the necessity of self-consistent thermal stability analysis for nanosheet-era 3D integration and provide a practical basis for reliability-aware early-stage system-technology co-optimization.