Improved device reliability for strain-balanced InP HBT growth on InPOSi

Abstract

Achieving low-cost high-volume production of InP-based technologies will require upscaling to large-diameter silicon fabrication compatible platforms. Thick high-quality III-V layers can be grown on engineered InP-on-Si substrates (InPOSi), if one considers strain-balancing of the entire III-V epitaxial stack at growth temperature to avoid relaxation and dislocation generation. Here, this concept is used to grow an InP HBT. The absence of a crosshatch pattern on the sample surface and a threading dislocation density at the same level as the one obtained for the reference epi stack grown on bulk InP (2 × 104 cm−2 in this work) in the device stack validates the successful implementation of the method. The DC characterization of devices fabricated on the strain-balanced stack shows similar values for all key electrical parameters as compared to devices fabricated on bulk InP. These results are further supported by reliability measurements where no sign of degradation is observed for these strain-balanced devices.