Defect-centric modeling of capacitance-voltage characteristics of SiGe/Si/SiGe heterostructures at cryogenic temperatures

Abstract

Understanding, modeling and prediction of semiconductor reliability at cryogenic temperature have become a popular research field in the last decade. One particular technology in this field are SiGe/Si/SiGe heterostacks, as they have become a popular platform for quantum devices. We have shown that the trapping in a SiGe/Si/SiGe heterostack can be studied with a phenomenological approach based on employment of effective charges at interfaces. Our approach is based on the assumption that the CV curves hysteresis originates from interface/border traps at the SiO2/Si-cap interface. To model the hysteresis and subsequent threshold voltage shift we use a fixed charge at the SiO2/Si-cap interface determining threshold voltage of the cap and for each stress voltage or stress time conditions, we introduce charges at the Si -QW/SiGe-top interface to match the threshold voltage of the quantum well. This methodology allows us to extract a cumulative effective charges stored in the traps after different stress conditions. Additionally, we extracted the distribution of the effective trapped charges over energy for a measurement sweep. The obtained distribution has distinct peak around 0.2 eV below the conduction band and peak concentrations of 4×1013cm−2eV−1. Our distribution profiles are in good agreement with the interface trap density of states reported in literature and this supports our hypothesis that the CV curve hysteresis is driven by interface traps.