Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node

Abstract

Complementary FET (CFET) is a promising device architecture that proceeds the CMOS scaling during the post-nanosheet device era. Among several CFET variants, Double-Row (DR) CFET further enables 15% track height scaling on standard cells, by sharing a middle row of vias, while sustaining an optimized Middle-Of-Line (MOL) process complexity. In this study, half-height double-row (hDR) CFET is proposed as a highly practical and impactful design style to overcome the cell and block level limitations of DR CFET architecture. First, hDR CFET introduces a high flexibility on standard cell layout design with significant area optimization. Secondly, hDR cell insertion in the backend physical design flow further optimizes the cell placement, and recovers block level area scaling to match the cell height scaling. Results on A7 CFET technology library show area reduction up to 50% on standard cell layouts. Moreover, block level PnR results after enabling only 6 types of hDR cells in standard cell library show 10% of area scaling on ARM Cortex-M0 32-bit core at 90% utilization, proving the strength of the concept. Finally, 14% of block level area scaling is further projected for an enriched standard cell library with an extended set of hDR cells.